During the design of an integrated circuit (IC), it is routine practice to determine whether the design can satisfy/survive numerous industry standard ESD tests. Usually, this check is performed after the IC layout is complete, meaning that if there is a significant issue with ESD sensitivity or another design concern, a designer may have to recreate a layout for the IC. It is very desirable to have software that will generally ensure satisfactory operation during ESD tests at various points in design process and well as perform other design “checks.”
To date, there are several software packages in existence that perform these types of analyses. These packages, however, perform static design “checks” using topology based search algorithms to find potential problems (i.e., ESD sensitivity) in a subject design. Completeness of these “checks” depends on the completeness of the defined topologies, and a subject design may not be considered “problem free” for alternative topologies that are not explicitly defined. Definition of such a large set of topologies, especially over a variety of technologies (i.e., CMOS or BiCMOS process technologies) is very difficult. Thus, there is a need for a software package with a greater search range.
Some other conventional methods and/or systems are: U.S. Pat. Nos. 5,689,432; 5,796,638; 6,058,492; 6,086,627; 6,493,850; 6,725,439; 6,810,509; 7,114,137; 6,907,589; 7,237,209; 7,243,317; 7,302,378; U.S. Patent Pre-Grant Publ. No. 2004/0243949; U.S. Patent Pre-Grant Publ. No. 2008/0148211; U.S. Patent Pre-Grant Publ. No. 2009;0094568; Zhan et al., “A technology-independent CAD tool for ESD protection device extraction: ESDExtractor,” Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p. 510-513, Nov. 10-14, 2002, San Jose, Calif.; Zhan et al., “ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction,” IEEE Tran. Computer-Aided Design, vol. 22, pp. 1362-1370, October 2003; and Zhan et al., “ESDInspector: A new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, pp. 1421, October 2004.